(1) Field of the Invention
This invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device in which a dual damascene method is used.
(2) Description of the Related Art
Minute semiconductor devices have been produced in recent years. The minuter semiconductor devices become, the narrower wiring width and a space between wirings get. Therefore, wiring resistance and parasitic capacitance between wirings increase. This will reduce signal speed and prevent semiconductor devices from operating at high speeds according to the scaling law.
In order to decrease wiring resistance and parasitic capacitance between wirings, methods for forming multilayer wirings, an insulating material, and a metal wiring material must be reviewed. Insulating materials with a small dielectric constant are effective in decreasing wiring capacitance. Moreover, to decrease wiring resistance, a metal wiring material is shifting from aluminum to copper with low resistivity.
It is difficult to apply conventional dry etching to fabricating copper films, so damascene methods are used. Damascene methods are divided broadly into a single damascene method and dual damascene method. With the single damascene method, plugs (vias) which connect a lower wiring and an upper wiring and wirings are formed by different processes. With the dual damascene method, plugs and wirings are formed at one time.
The minuter semiconductor devices become, the greater the number of wiring layers in them gets. For example, the number of wiring layers in semiconductor devices which belong to a generation having a wiring width of 0.18 μm is six. In this case, similar processes are repeated, for example, twelve times (six times for forming wirings and six times for forming plugs) in the single damascene method. On the other hand, similar processes are repeated only six times in the dual damascene method.
As described above, wirings and plugs can be formed at one time in the dual damascene method. As a result, the number of processes in the dual damascene method is half of that of processes in the single damascene method. Therefore, to lower production costs and improve production efficiency, it is advantageous to adopt the dual damascene method. Furthermore, with the dual damascene method, contact resistance between a lower wiring and a plug connected thereto is low and it is easy to avoid bad contact between them. As a result, the reliability of wirings will improve.
FIGS. 8(A) through 8(M) are views showing a method for fabricating a semiconductor device in which a conventional dual damascene method is used. A plurality of films, such as an insulating film and metal film, are formed first on a lower wiring layer according to FIGS. 8(A) through 8(C). The lower wiring layer is made in the following way.
First, a silicon dioxide film (SiO2 film) 22, organic insulating film 23, and silicon dioxide film 24 are formed on a silicon substrate 21. In this case, the silicon dioxide film 22 with a thickness of 200 nm and the silicon dioxide film 24 with a thickness of 100 nm are formed by a plasma CVD method.
The organic insulating film 23 with a thickness of 400 nm is formed by the use of, for example, Allied-Signal's FLARE 2.0, being an insulating material having a low dielectric constant, by a spin coat method. Allied-Signal's FLARE 2.0 is an aromatic polymer with a dielectric constant of 2.8 lower than 4.1, being the dielectric constant of a silicon dioxide film, and can withstand temperatures higher than 400° C. In this example, Allied-Signal's FLARE 2.0 is used as the organic insulating film 23. However, Dow Chemical's SILK, being a hydrocarbonaceous polymer, or the like can be used. Another substance, such as resin which contains hydrocarbon, fluorine, or the like, may be used as material for the organic insulating film 23.
To form a first wiring layer in the organic insulating film 23 and silicon dioxide film 24 formed in this way, first the silicon dioxide film 24 is coated with a photoresist film, being a photosensitive polymer, and a window for a wiring pattern is formed through exposure treatment and development treatment. An opening of a wiring shaped pattern is made in the silicon dioxide film 24 through this window by etching, such as a plasma etching method. Then a portion of the organic insulating film 23 which is exposed from the opening for a wiring in the silicon dioxide film 24 is removed by a plasma etching method to make an opening of a wiring shaped pattern. The organic insulating film 23 is etched in an atmosphere where O2 gas and Ar gas are introduced. An etchant used in this case is oxygen, so the organic insulating film 23 and photoresist film are etched selectively in relation to the silicon dioxide films 22 and 24 and the silicon dioxide film 24 is not etched. However, the photoresist film is etched by oxygen, so the etching of the organic insulating film 23 and the removal of the photoresist film can be performed at one time.
A wiring trench in the first wiring layer consists of the opening in the silicon dioxide film 24 and the opening in the organic insulating film 23 formed through the above patterning treatment. The opening in the organic insulating film 23 is right beneath the opening in the silicon dioxide film 24.
Next, a barrier metal film 25 of TiN or TaN, the melting point of which is high, with a thickness of 50 nm is formed by sputtering on the inner surface of the wiring trench formed in this way and the surface of the silicon dioxide film 24 and then a copper (Cu) film 26 with a thickness of 800 nm is formed in the same way on the barrier metal film 25 by sputtering.
There will be irregularities on the surface of the copper film 26. Therefore, to flatten the surface of the copper film 26, anneal treatment is performed on the copper film 26 at 400° C. in an atmosphere of hydrogen at a pressure of 0.1 torr for five minutes. As a result of this anneal treatment, the copper film 26 will completely be buried in the wiring trench.
Then the copper film 26 is polished by a chemical mechanical polishing (CMP) method to leave the copper film 26 only in the wiring trench. This copper film 26 is the first wiring layer.
By performing the above treatment, a structure shown in FIG. 8(A) will be obtained.
Subsequently, as shown in FIG. 8(B), a plurality of films, such as insulating films and metal films, described below are formed on the copper film 26 and silicon dioxide film 24. That is to say, a silicon nitride film 30 with a thickness of 50 nm is formed on the copper film 26 and silicon dioxide film 24 by a plasma CVD method. A silicon dioxide film 31 with a thickness of 600 nm is formed on the silicon nitride film 30 by a plasma CVD method. Moreover, an organic insulating film 32 with a thickness of 400 nm is formed on the silicon dioxide film 31 by a spin coat method. In this case, one of the above materials used for the organic insulating film 23 is selected for forming the organic insulating film 32.
Then a silicon dioxide film 33 with a thickness of 100 nm is formed on the organic insulating film 32 by a plasma CVD method. A silicon nitride film 34 with a thickness of 100 nm is formed on the silicon dioxide film 33 by a plasma CVD method.
After the above films being formed, as shown in FIG. 8(C), the silicon nitride film 34 is coated with a photoresist 35 and exposure treatment and development treatment are performed on the photoresist 35 to form a window. An opening for a wiring 34a having a shape corresponding to a second wiring layer is made in the silicon nitride film 34 by a photolithographic method in which the photoresist 35 is used as a mask (see FIG. 8(D)).
Then the photoresist 35 is ashed by oxygen plasma and is removed. As shown in FIG. 8(E), the surface of the silicon nitride film 34 and the inside of the opening 34a are coated with a photoresist film 36 and exposure treatment and development treatment are performed on the photoresist film 36 to form a window, which is in the opening for a wiring 34a and which is opposite to part of the first wiring layer, in the photoresist film 36. This window has a shape corresponding to a contact via. Then, as shown in FIG. 8(F), the silicon dioxide film 33 is etched through the window in the photoresist film 36 to make an opening 33a having a shape corresponding to the contact via.
As shown in FIG. 8(G), anisotropic plasma etching with oxygen and argon is performed on the organic insulating film 32 through the opening 33a after the above etching to form an opening 32a there. By performing this etching, the photoresist film 36 is also etched and removed. Therefore, the process for removing only the photoresist film 36 is unnecessary and the organic insulating film 32 will not be etched unnecessarily.
Subsequently, as shown in FIG. 8(H), the silicon dioxide film 33 is etched through the opening 34a into the shape of a wiring by plasma etching using gas which contains fluorine with the silicon nitride film 34 as a mask to make an opening 33b. During this etching the organic insulating film 32 is used as a mask and the silicon dioxide film 31 beneath it is also etched through the opening 32a in the organic insulating film 32. As a result, an opening 31a is made in the silicon dioxide film 31 simultaneously with the opening 33b. 
Then the organic insulating film 32 is etched through the opening 34a in the silicon nitride film 34 into the shape of the wiring by oxygen plasma. As a result, an opening for a wiring 32b shown in FIG. 8(I) is made there. The opening for a wiring 32b in the organic insulating film 32, together with the opening for a wiring 33b in the silicon dioxide film 33, will be used as a wiring trench in the second wiring layer.
Subsequently, as shown in FIG. 8(J), plasma etching is performed on the silicon nitride film 30 beneath the opening 31a by the use of C4F8 gas and O2 gas with the silicon dioxide film 31 as a mask to make an opening 30a there. The opening 30a in the silicon nitride film 30 and the opening 31a in the silicon dioxide film 31 are used as a contact via hole and part of wirings on the first wiring layer will get exposed in the bottom of the contact via hole.
Subsequently, as shown in FIG. 8(K), a barrier metal film 37 of TiN or TaN with a thickness of 50 nm is formed by sputtering on the inner wall of a concave portion formed in the above way.
Subsequently, as shown in FIG. 8(L), the lower half of a copper film 38 with a thickness of 100 nm is formed by sputtering and the upper half of the copper film 38 with a thickness of 1500 nm is formed on it by an electroplating method. Then anneal treatment is performed on the copper film 38 at 400° C. in an atmosphere of hydrogen for thirty minutes. As a result of this anneal treatment, particles in the copper film 38 will grow and the reliability of wirings will improve.
Subsequently, as shown in FIG. 8(M), the copper film 38 is polished by a CMP method to leave the copper film 38 only in the wiring trench in the second wiring layer and the contact via hole. A copper film in the wiring trench in the second wiring layer (the upper half of the copper film 38) is used as a wiring and a copper film left in the contact via hole (the lower half of the copper film 38) is used as a plug.
One of the problems caused by adopting the dual damascene method is defective burying of the copper film 38. Raising the coverage of the barrier metal film 37 is considered as a measure to cope with this problem.
By the way, the coverage of the barrier metal film 37 depends on a shape into which a wiring trench or connection hole is fabricated. For example, if a side etch occurs in the silicon nitride film 30, an overhang will appear in a connection hole. As a result, when the copper film 38 is formed, a void 40 shown in FIG. 9 will be created.
A side etch in the silicon nitride film 30 is corrosion caused by the reaction between reaction products (fluoride expressed by CFx) which are produced when the silicon nitride film 30 is etched and the silicon nitride film 30. If after etching the silicon nitride film 30 is left in the air as it is, then moisture in the air will accelerate this corrosion. The reason for this is as follows. Hydrogen fluoride (HF) is produced from fluorine (F) contained in the reaction products CFx and moisture in the air and corrosion occurs. Then a layer which has changed in quality due to the reaction is removed by wet cleaning in the next process.
FIGS. 10(A), 10(B) and 11 are views for describing the cause of the occurrence of the side etch. As shown in FIG. 10(A), it is assumed that time from the etching of the silicon nitride film 30 to wet cleaning is TIME#1, that time from the wet cleaning to the checking, that is to say, the measuring of its section is TIME#2, and that time from the etching of the silicon nitride film 30 to the checking of its section is TIME#3.
In this case, with condition A TIME#1, that is to say, time from the etching of the silicon nitride film 30 to wet cleaning is set to 0 hour and TIME#2, that is to say, time from the wet cleaning to the checking of its section is set to 0 hour. With condition B TIME#1 and TIME#2 are set to 0 hour and 6 hours respectively. With condition C TIME#1 and TIME#2 are set to 6 hours and 0 hour respectively. With the last condition D TIME#1 and TIME#2 are arbitrary and TIME#3 is set to 9 hours.
FIG. 11 is a view showing the width of a side etch which occurs under each condition. As shown in FIG. 11, a side etch is observed only under condition C and is not observed under the other conditions. This shows that a side etch occurs according to the length of time from the etching of the silicon nitride film 30 to wet cleaning.
Conventionally, to prevent corrosion, time after etching the silicon nitride film 30 and before wet cleaning treatment must be managed or semiconductor substrates must be kept in a container filled with dry nitrogen (N2) However, this is troublesome.